The present invention relates generally to a microcomputer. More specifically, the invention relates to improved instruction cycling in a microcomputer for speeding up microcomputer processing.
Modern monolithic microcomputers often employ a pipe-line architecture which allows fetch cycles and instruction execution cycles to overlap, in other words, each such fetch cycle for fetching any part of an instruction from memory does not overlap with the execution of that same instruction, such execution occuring in a following cycle. Each fetched instruction consists of an operation code (OP code) which is stored in a read-only-memory (ROM), such as a programmable read-only-memory (PROM), and an operand, also stored in the ROM, which may point to a variable value stored in a random-access memory (RAM). In conventional pipe-line architectures, the OP code fetch and the operand fetch are performed in the execution cycles for different instructions, each of which is hereafter referred to generally as an "instruction cycle" or more specifically as one or more "machine cycles". For example, in order to fetch a 2-byte instruction including a 1-byte OP code and a 1-byte operand in a 4-bit microcomputer (in the case of four bits per byte), 2 instruction cycles are required. The same applies to an 8-bit machine with eight bits per byte, as discussed below. Therefore, in this case, the performance of each instruction requires three machine cycles or, in the more general and less precise terminology above, three instruction cycles.
As is clear, the execution of each instruction includes the fetching of the OP code then of each operand in sequence, and then the execution itself. Generally, a series of machine cycles are involved with the fetching of the operand part of the instruction and the execution of the instruction, in which the fetching of the OP code byte overlaps with the execution of the preceding instruction in the conventional pipeline processor. This conventional pipe-line architecture is not satisfactorily efficient.